1. Field of the Invention
The present invention relates generally to a nonvolatile memory device, and relates more specifically to an improved metal-oxide-nitride-oxide-semiconductor (MONOS) memory device.
2. Description of the Related Art
One type of nonvolatile memory device is the metal-oxide-nitride-oxide-semiconductor (MONOS) memory device. One characteristic of a MONOS memory device is that the gate insulation layer between the channel region and control gate is a silicon oxide-silicon nitride-silicon oxide layer, and electric charges are trapped in the silicon oxide layer.
FIG. 6 is a partial sectional drawing of a MONOS type nonvolatile memory device according to the related art. In a MONOS type memory cell 100 the source region 101a and drain region 101b are formed in the semiconductor substrate 101 separated by a channel formation region disposed therebetween. A control gate (CG) 103 is formed over the channel region through an intervening gate insulation layer 104. The gate insulation layer 104 has three layers, a first layer 104a that is a silicon oxide layer formed on the semiconductor substrate 101, a second layer 104b that is a silicon nitride layer formed on the first layer 104a, and a third layer 104c that is a silicon oxide layer formed on the second layer 104b. The gate insulation layer 104 is structured to have a trap level in the second layer 104b. 
With this memory device, electrons hopping into the first layer 104a are trapped at the trap level of the second layer 104b. Electrons that enter and are trapped at the trap level cannot easily escape from the trap level, and thus stabilize.
Because electrons, or more specifically negatively charged particles, are held in the gate insulation layer 104, and more precisely in the second layer 104b, at this time, the threshold value of the gate insulation layer 104 rises compared with the initial level. Whether or not data was written is determined by detecting change in this threshold value, and operation as a memory device is thus achieved.
Japanese Patent Laid-Open Publications (kokai) 2001-102466 and 2001-148434, and U.S. Pat. No. 6,255,166B1 teach a nonvolatile memory device of a so-called xe2x80x9csplit gatexe2x80x9d type as an improvement of this MONOS type memory device.
FIG. 7 shows a split-gate nonvolatile memory device according to the related art. The nonvolatile memory device shown in FIG. 6 stores one bit of data in one memory cell, but the split-gate memory device shown in FIG. 7 can store two bits of data in one memory cell.
In FIG. 7 a first impurity region (n-type) 201a and a second impurity region (n-type) 201b are formed in a p-type semiconductor substrate 201 separated by a channel formation region therebetween. This split gate memory cell 200 has a word gate (denoted xe2x80x9cWGxe2x80x9d in the figures) 203 formed on the semiconductor substrate 201 through an intervening first gate insulation layer 202. A first control gate (denoted xe2x80x9cLCGxe2x80x9d in the figures) 204 and a second control gate (denoted xe2x80x9cRCGxe2x80x9d in the figures) 205 are formed as sidewalls on opposite sides of the word gate WG 203. A second gate insulation layer 206a is disposed between the bottom of the first control gate LCG 204 and semiconductor substrate 201. A first side insulation layer 207a is disposed between the side of first control gate LCG 204 and word gate WG 203. A third gate insulation layer 206b is likewise disposed between the bottom of second control gate RCG 205 and the semiconductor substrate 201, and a second side insulation layer 207b is disposed between the side of second control gate RCG 205 and the word gate WG 203.
The second and third gate insulation layers 206a and 206b, and the first and second side insulation layers 207a and 207b have three layers, a first layer that is a silicon oxide layer formed on the semiconductor substrate 201, a second layer that is a silicon nitride layer formed on the first layer, and a third layer that is a silicon oxide layer formed on the second layer.
Compared with the memory device shown in FIG. 6, the split gate memory device shown in FIG. 7 is more complex structurally, but is a symmetrical structure that can record two bits.
Writing to the above split gate memory device is described first below using by way of example for simplicity writing to the second control gate RCG 205 side of this memory cell 200.
A specific voltage is applied to the second impurity region (drain region) 201b, word gate WG 203, first control gate LCG 204, and second control gate RCG 205. Of the electrons that move from the first impurity region (source region) 201a to the drain region 201b, the hot electrons, that is, the electrons with high kinetic energy, hop into the third gate insulation layer 206b due to the voltage applied to the second control gate RCG 205, and data is thus written.
Erasing data is accomplished as follows. By applying a specific voltage to the drain region 201b and second control gate RCG 205, a hole is created by the tunnel effect in the neighborhood of the channel formation region of the drain region 201b. This hole is a hot hole, that is, a hole trapping high kinetic energy, and jumps into the third gate insulation layer 206b. If an electron is trapped at the trap level in the silicon nitride layer (second layer) at this time, the electron and hole couple and die. That is, the charge is depleted and the initial state is restored. This is called the BBH (band-to-band) tunneling hole erasing mechanism, i.e., a method of erasing by band-to-band tunneling.
The initial state is restored as a result of electron-hole bonding as described above, but it is important to note that in order for this to happen the electron and hole must be injected to the same spatial location. This is because the silicon nitride layer is an insulator and the carriers (electron and hole) cannot move through the silicon nitride layer structure and bond again.
Writing with a hot electron occurs near the word gate WG 203 in the split gate memory device shown in FIG. 7.
Erasing by means of the BBH erase mechanism, however, occurs at the edge of the drain, that is, near the edge part of the drain region 201b. 
In other words, even if the total charge trapped at the trap level in the silicon nitride layer of the device shown in FIG. 7 is 0, residual positive and negative charges remain stored in a charge trapping region. Furthermore, because a charge causing these charges to cancel each other out is not supplied, they gradually increase through repeated write and erase cycles.
When an unbalanced charge thus remains internally, there is a significant drop in the mutual conductance of the MOS transistors. Furthermore, this is a significant problem with respect to the structure of rewritable memory because this drop in conductance changes as the write and erase cycles repeat.
To solve this problem a nonvolatile memory device according to one aspect of the present invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a first control gate formed to one side of the word gate with a first side insulation layer therebetween; a second control gate formed to another side of the word gate with a second side insulation layer therebetween; a second gate insulation layer having a charge trapping region formed between the substrate and the first control gate; and a third gate insulation layer having a charge trapping region formed between the substrate and second control gate. With this configuration, the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and first control gate is lower within a first, range in the gate length direction adjacent the first side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.
Preferably, the magnitude of an electric field applied in a direction orthogonal relative to the substrate surface between the substrate and second control gate is lower within a third range (e.g., within L1) in the gate length direction adjacent the second side insulation layer than it is within a fourth range (e.g., within L3) in the gate length direction closer to the second impurity region.
A nonvolatile memory device according to another aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a first control gate formed to one side of the word gate with a first side insulation layer therebetween; a second control gate formed to another side of the word gate with a second side insulation layer therebetween; a second gate insulation layer having a charge trapping region formed between the substrate and the first control gate; and a third gate insulation layer having a charge trapping region formed between the substrate and second control gate. In this configuration, the film thickness of the second gate insulation layer is thicker within a first range in the gate length direction adjacent the first side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.
Preferably in this case the film thickness of the third gate insulation layer is thicker within a third range in the gate length direction adjacent the second side insulation layer than it is within a fourth range in the gate length direction closer to the second impurity region.
A nonvolatile memory device according to a another aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a first control gate formed to one side of the word gate with a first side insulation layer therebetween; a second control gate formed to another side of the word gate with a second side insulation layer therebetween; a second gate insulation layer having a charge trapping region formed between the substrate and the first control gate; and a third gate insulation layer having a charge trapping region formed between the substrate and second control gate. In this configuration the second gate insulation layer is a multiple layer film having a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer of the second gate insulation layer being in contact with the first control gate within a first range in the gate length direction in proximity to the first impurity region.
Preferably in this case the third gate insulation layer is a multiple layer film having a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer of the third gate insulation layer being in contact with the second control gate within a second range in a gate length direction in proximity to the second impurity region.
A nonvolatile memory device according to a further aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a control gate formed to one side of the word gate with a side insulation layer therebetween; and a second gate insulation layer having a charge trapping region formed between the substrate and the control gate. The magnitude of the electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and control gate is lower within a first range in the gate length direction adjacent the side insulation layer than it is within a second range in the gate length direction closer to the second impurity region.
A nonvolatile memory device according to a still further aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a control gate formed to one side of the word gate with a side insulation layer therebetween; and a second gate insulation layer having a charge trapping region formed between the substrate and the control gate. The film thickness of the second gate insulation layer is thicker within a first range in the gate length direction adjacent the side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.
A nonvolatile memory device according to another aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a control gate formed to one side of the word gate with a side insulation layer therebetween; and a second gate insulation layer having a charge trapping region formed between the substrate and the control gate. The second gate insulation layer is a multiple layer film having a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer of the second gate insulation layer being in contact with the control gate in a range in the gate length direction in proximity to the second impurity region.
A nonvolatile memory device according to yet another aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; and a control gate formed above the channel region with a gate insulation layer therebetween. The electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and control gate is lower within a middle region in the gate length direction of the control gate than it is in regions closer to the first and second impurity regions.
A nonvolatile memory device according to still another aspect of the invention has first and second impurity regions formed in a substrate with a channel region therebetween; and a control gate formed above the channel region with a gate insulation layer therebetween. The gate insulation layer is a multiple layer film having a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer of the second gate insulation layer being in contact with the control gate in proximity to the first and second impurity regions.
Thus comprised, the invention provides a MONOS type nonvolatile memory device capable of withstanding repeated write/erase cycles.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.